This specification relates to manufacturing polishing pads useful for polishing and planarizing semiconductor, optical and magnetic substrates.
Polyurethane polishing pads are the primary pad-type for a variety of demanding precision polishing applications. These polyurethane polishing pads are effective for polishing silicon wafers, patterned wafers, flat panel displays and magnetic storage disks. In particular, polyurethane polishing pads provide the mechanical integrity and chemical resistance for most polishing operations used to fabricate integrated circuits. For example, polyurethane polishing pads have high strength for resisting tearing; abrasion resistance for avoiding wear problems during polishing; and stability for resisting attack by strong acidic and strong caustic polishing solutions.
The production of semiconductors typically involves several chemical mechanical planarization (CMP) processes. In each CMP process, a polishing pad in combination with a polishing solution, such as an abrasive-containing polishing slurry or an abrasive-free reactive liquid, removes excess material in a manner that planarizes or maintains flatness for receipt of a subsequent layer. The stacking of these layers combines in a manner that forms an integrated circuit. The fabrication of these semiconductor devices continues to become more complex due to requirements for devices with higher operating speeds, lower leakage currents and reduced power consumption. In terms of device architecture, this translates to finer feature geometries and increased metallization levels. In some applications, these increasingly stringent device design requirements are driving the adoption of increased number of tungsten interconnect plugs or vias in conjunction with new dielectric materials having lower dielectric constants. The diminished physical properties, frequently associated with low k and ultra-low k materials, in combination with the devices' increased complexity have led to greater demands on CMP consumables, such as polishing pads and polishing solutions.
In order to maintain consistent wafer throughput, semiconductor fabricators have practiced in-situ conditioning with diamond disks for years. In-situ conditioning cuts the polishing pads top surface during polishing. A one-hundred percent in-situ conditioning process diamond-conditions during the entire polishing process. A fifty-percent in-situ conditioning process conditions over one-half the polishing process. This conditioning process is essential to roughen the polishing surface to maintain removal rate by preventing glazing of the polishing pad. In addition, these pads must polish with consistent rates over hundreds of wafers.
Casting polyurethane into cakes and cutting the cakes into several thin polishing pads has proven to be an effective method for manufacturing polishing pads with consistent reproducible polishing properties. Reinhardt et al., in U.S. Pat. No. 5,578,362, disclose the use of polymeric microspheres to improve planarization while maintaining low defectivity. Unfortunately, commercial polyurethane pads produced with this structure often have rates that are sensitive to the diamond conditioner and conditioning process. In particular, as the diamonds wear on the conditioner, they cut shallower channels into the polishing pad and these shallower channels can result in lower polishing removal rates.
In interlayer dielectric (ILD) polishing with fumed silica slurry, removal rate (RR) of a polishing pad is very sensitive to diamond conditioning. Without in-situ conditioning, the RR deteriorates rapidly within a few wafers of polishing, see FIG. 1. Although one-hundred percent in-situ conditioning is typically used in ILD polishing with a fumed silica slurry, high RR sensitivity to conditioning can still result in performance variation as a result of wear of conditioning disk over pad life. Therefore, there is a need for a polishing pad with reduced sensitivity to conditioning without sacrificing its polishing efficiency. Furthermore, there is a need to develop an effective method for manufacturing these and other CMP polishing pads.